1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly to a solid state memory having a latch circuit in which a chip address on a printed circuit board (PCB) or a system is stored on a flash memory cell in a solid state memory device having a plurality of memory chips and serial buses in order to reduce the number of chip pads, thereby lowering the cost and the number of pins to reduce poor throughput and also to simplify the circuit on the substrate.
2. Description of the Prior Art
Generally, as higher degree of integration is required for a memory device, a product has been developed in which a plurality of memory chips are included into a single memory device. In this case, it is more cost effective to construct the bus structure of this memory device as a few serial bus structure rather than a plurality of parallel bus structure so that it makes the printed circuit board thereof more simplified.
However, since commands, and addresses and data are commonly transmitted to the plurality of chips, it is extremely important to confirm respective chips and addresses.
FIG. 1 shows a memory module of a conventional solid state memory, in which a plurality of memory chips 2, and address pads 4 using the address received from outside as an input to select the memory chips are mounted on a printed circuit board 1. In FIG. 1, address pins 3 are connected between the memory chips 4 and the address pads 4. Also, the memory chips 2 are connected to a common serial bus 5. The address pins 3 of the memory chips 2 are fixed to the address pads 4 on the printed circuit board 1 to recognize the address of each of the memory chips 2. Address such as the power supply Vcc and the ground Vss, which are supplied to the address pads 3, may expressed into "1" and "0", respectively, for convenience of explanation.
FIG. 2 shows a conventional confirmation circuit diagram of confirming commands and data inputted to a common serial bus when eight (8) memory chips are mounted on the memory module. The circuit serves to confirm commands and data inputted via the common serial bus 5 commonly connected to each of the memory devices, in case that eight (8) memory chips 2 are mounted on the memory module on the printed circuit board 1. In this case, each of the memory chips 2 requires three (3) address pins 3, and the address of the memory chip 2 represented in the address latch means 10 of FIG. 2 is "110", which represents the sixth memory chip in the memory chip. At this time, if the address of the memory chip 2 is inputted to the serial input terminal 6 via the serial bus 5 along with the clock signal CK and the chip select signal CS. The input address is supplied to the comparator 9 via the three signal lines 8 through the shift register 7.
Also, the address of the memory device, which is inputted from the address latch means 10 via the address pads 4 on the printed circuit board 1, is supplied to the comparator 9. The comparator 9 confirms whether the two addresses are identical or not. If so, it drives a corresponding memory chip.
However, this conventional technology requires that three address pads and three address pins be mounted on a single printed circuit board if eight memory devices are mounted on it. Thus, it has disadvantages in that the circuit on the printed circuit board on which the memory devices are mounted, becomes complicated and the productivity is lowered due to defects of the address pins during the process of package or when the memory chips are mounted on the printed circuit board.